Provartec develops EDA tools for HDL automation and designs Soc IPs based on this technology. We introduce RobustVerilog, an object-oriented HDL language, taking VLSI design a giant leap forward. Our powerful tools allow any design to become constructable, parametric and adaptable to changes. The bottom line is that our tools save time, improve code confidence and allow reuse of code. 

We are proud to publish and maintain free IP cores, in cooperation with OpenCores.org; these cores demonstrate the versatility of our technology. 

You are welcome to register and join the RobustVerilog user comunity becoming part of the next VLSI evolution.